The present invention is directed to circuit testing. It is particularly applicable to testers for testing digital circuits to which signals must be applied at a rapid rate.
The increasing complexity of digital circuits has increased the difficulty of testing them. In order to test such circuits adequately, signals must be applied to and sensed at a large number of circuit terminals simultaneously. The set of signals simultaneously applied or expected is commonly referred to as a vector, and a large string of vectors must be applied in sequence to test complex circuits adequately. Because each vector has a large number of components, and because the number of vectors is large, the memory needed to store a test program in a tester is expensive.
Contributing to this expense is the fact that the complicated digital circuits often consist of dynamic devices, which must be tested at a high rate of speed in order to function properly. This reduces the memory access time that can be tolerated, and memories with lower access times tend to be more expensive.
In light of this expense, certain schemes have been used in the past to reduce memory speed requirements. In many testers, for instance, the memory is several times as "wide" as the required vector. That is, enough information is stored at a single memory address to generate many vectors. A single memory access time is thus spread over many vectors. This multiplies the effective speed of vector retrieval without increasing the cost of the individual memory elements. When information is retrieved from the memory, it is stored briefly in intermediate registers from which the information is read rapidly one vector at a time. The result is that only the intermediate registers have to be especially fast; the large main memory, which causes the most expense, can be several times slower than the registers.
A further way to reduce memory cost is to design tests so that certain strings of vectors are used more than once. If such a test is used in a system that can jump between locations in memory instead of reading the contents from the memory locations strictly in the order of their addresses, certain portions of the memory can be used over and over again within the same test, thereby reducing the size and cost of the needed memory.
Although the ability to jump from memory location to memory location does reduce the size of the memory, some of the attendant reduction in memory expense is compromised because this type of organization places certain constraints on memory speed. Specifically, the access time must be low enough that the time taken to refill the intermediate tester registers after a jump does not delay retrieval of a vector from the registers by more time than can be tolerated between applications of vectors to the unit under test. Unless the tester stores all of the vectors in its memory one after another in the order in which they are to be applied, therefore, there has in the past been a lower limit on the speed of the memory that can be used.
Accordingly, an object of the present invention is to use relatively low-speed tester memories while permitting jumps from point to point in a memory so that portions of its contents can be reused.